Highly integrated semiconductor circuits are increasingly important, particularly in the field of producing battery operated devices such as cell phones, portable computers such as laptops, notebook and PDAs, wireless email terminals, MP3 audio and video players, portable wireless web browsers and the like, and these integrated circuits increasingly include on-board data storage. As is known in the art, such storage may take the form of dynamic memory in which arrays of storage cells are provided, each cell is a storage capacitor formed with an adjacent access transistor. Dynamic memory (“DRAM”) offers excellent circuit density and is often provided as fast access memory for a processor, such as a first level cache memory or scratchpad memory. In the prior art it is known to produce these DRAMs as stand alone integrated circuits using dedicated semiconductor process techniques that are specifically optimized to produce space and power efficient DRAM devices.
As semiconductor process technology advances have occurred, process fabrication technology has enabled the DRAM to be incorporated into large, highly integrated ICs, sometimes called “SOCs” or “systems on a chip.” Typical applications for these embedded DRAMs or “e-DRAM” include for use as fast memory adjacent a processor such as cache memory, as fast scratchpad memory, or to reduce or eliminate the need for discrete DRAM devices. Portable devices are particularly important applications of highly integrated ICs, or SOCs. These devices include cell phones, pocket PCs, PDAs and the like.
FIG. 1 depicts a typical prior art memory cell 11. For a dynamic memory cell such as is commonly used, an access transistor (Ts) couples a data line (DL),sometimes referred to as a bit line or “BL”, in response to a control voltage on a gate terminal of the access transistor, to a storage capacitor (Cs) which is coupled between the access transistor and a voltage (Vs). The voltage used as the potential for the storage capacitor can be a ground or a positive voltage, depending on the particular design of the DRAM as is known in the art. The gate of the access transistor Ts is coupled to one of a plurality of lines called word lines (WL), often referred to as “row lines” or “rows.” These lines are conventionally routed across the DRAM array in row or column fashion and referred to as row lines. A typical DRAM will have many thousands of the memory cells 11 depicted. The cells will be arranged in one or more arrays and typically the bit lines or data lines DL will be arranged in a plurality of spaced columns, typically but not always perpendicular to the word lines or row lines arranged in a plurality of rows.
The storage capacitor may be fabricated in many ways. In the prior art planar capacitors have been used, more recently crown shaped capacitors formed above the access transistors in insulating and metal layers have been used to further increase the density (number of bits per unit of silicon area) of the arrays. Alternate implementations where the capacitors are formed as a trench formed into the substrate adjacent the access transistors are known in the art and are likewise used to increase capacity per silicon area.
The storage capacitor Cs of FIG. 11 may be used to hold a charge representing a logical data value. The voltage that corresponds to the charge stored may be assigned a logical ‘1’ or a logical ‘0’ depending on the design approach used for the particular DRAM. The voltage at cell node CN corresponds to the voltage across the storage capacitor. The storage capacitor is written by a control circuit coupling a data value for storage onto the bit line BL while the access transistor for the particular cell is simultaneously activated by placing the appropriate voltage on the control gate of the access transistor Ts, that is the word line WL associated with the memory cell 11 has a control voltage on it. To read the value, the access transistor is activated while no voltage or a simple bias level is placed on the bit line BL and the capacitor discharges through the access transistor to place a stored voltage on the bit line, which is then coupled to a sense amplifier (not visible) where the level is sensed and amplified to the appropriate voltage representing a logical value, this voltage is then coupled through input/output (I/O) circuitry that is connected to the data line DL to make the read data available for use.
Because the storage capacitor Cs has an inherent leakage current, the memory cell 11 must be periodically refreshed by control circuitry. The refresh cycle may be controlled by an external processor; more often in current memory products an on-board controller will periodically refresh the storage capacitors. The refresh is a read and write back access cycle that reads the stored values from a plurality of the memory cells which require refreshing (determined based on the time that has passed since the last refresh or access cycle), the stored data is read out, amplified by sense amplifiers, and written back into the cells. Because the storage cells of a one transistor or 1T cell such as memory cell 11 require refreshing to maintain a stored value, the memory implemented using such cells is referred to as “dynamic” memory. Dynamic memory requires more control circuitry than a static memory, such as an SRAM, but the small size of the DRAM cell allows many more bits of storage to be implemented per unit of silicon area than for a corresponding SRAM cell. Nonvolatile memory may also be used to store data, such as EEPROM, FLASH, and the like; these memories also require control circuitry and the cells are larger in area than the DRAM cell 11. These other memory types do not require refreshing and are often referred to as “non-volatile” memory cells. Importantly, a dynamic memory will lose the data in the absence of a power supply, while a non-volatile memory will retain the data. Static RAM cells are basically made up of transistor latches and therefore will retain the data so long as power is present but not in the absence of power. One method to make an SRAM, which has the advantage of a very rapid access time, act as a non-volatile memory is to use a battery backed up SRAM, so that the battery maintains power to the memory in the absence of system power. The DRAM has the best density and so is the preferred memory type for data storage of any substantial amount.
FIG. 2 depicts in a plan view a block diagram of a DRAM array of the prior art using many memory cells such as the one illustrated in FIG. 1. In DRAM 31, a plurality of memory cell arrays 35 is provided each having a plurality of memory cells 11 inside. The memory cells are arranged as rows and columns, with each column being associated with one bit of a data word, the I/O buffers 39 couple the data lines (not shown) which run in a columnar direction, to a data bus. Word line decoders 33 activate the word line associated with a row of the memory cells within the arrays 35 responsive to an address value. Each array of cells is coupled to a sense amplifier which receives two data lines, usually called bit line or BL and a complementary bit line or ZBL. In FIG. 2 a single memory bank is shown so only one pair of bit lines is coupled for each column. Control logic 41 provides the various signals to the sense amplifiers 37 and the I/O buffers 39 to cause the data presented at the I/O ports to be written to the appropriate row of memory cells, or, to cause stored data to be read from the appropriate row of memory cells to output data from the I/O buffers 39. All of these operations and the circuits required are well known in the art.
FIG. 3 depicts a plan view of a block diagram of a further prior art embodiment of a DRAM array which uses segmented bit lines or data lines to share the sense amplifiers between two banks of memory cells. In FIG. 3, DRAM array 51 includes a memory bank 0 which is an upper memory bank and has memory cell arrays 55 that include memory cells as shown in FIG. 1 arranged in rows and columns, each memory cell array 55 having a pair of bit lines or data lines BL and ZBL, word line decoders 53 provide the appropriate voltage on the appropriate word line or row lines (not shown) for reading and writing an addressed row of memory cells. Sense amplifiers 57 are shared between the upper memory bank 0 and the lower memory bank 1. A second word line decoder circuit 53 for bank 1 is depicted in the lower portion of the diagram and this word line decoder provides the required word line signals for addressing a row of memory cells in the memory arrays 59 of bank 1. The data lines or bit lines from bank 1 are also selectively coupled to the same sense amplifiers 57 for each column in an architecture known as “segmented” bit lines. Although only two memory banks are illustrated, many more may be provided. A complete DRAM of the prior art may include thousands or even millions of cells in a single device. I/O buffers 61 then provide output data to a data bus, or input data from a data bus, to couple the DRAM. The address lines are decoded to select the active row and the portion of the columnar bit line that is to be used for a particular cycle. Column address circuitry selects the correct column and segment based on the values of the address bits.
The arrangements of DRAM cells shown in FIG. 2 and FIG. 3 may depict the major blocks of a typical DRAM integrated circuit. However increasingly DRAM circuits are being embedded into application specific integrated circuits (ASICS), so called SOCs or “System on a chip” devices, custom integrated circuits and the like. FIG. 4 depicts, in one typical prior art arrangement, the major blocks of an ASIC IC1 with an embedded DRAM block A. In addition to the embedded DRAM, IC1 includes I/O buffers, an embedded SRAM block B which may be used as a register file, for example, a microprocessor core which could implement a programmable processor, a digital signal processor (DSP), or other known processors such as a RISC machine and the like. In addition to these core or predetermined functions, a section of user defined logic is shown. In this area a designer may implement functions that optimize the circuit for a specific use, such as for a PDA, digital camera, cell phone, music player, radio, or other application as is known in the art.
The use of improved semiconductor processing technology makes embedding DRAM and other memory blocks more and more attractive in current ASIC or semi-custom IC manufacture. Improved isolation and buried layer techniques, coupled with advanced photolithographic techniques, and asymmetric processing of different regions of the integrated circuit, make it possible to provide the smaller transistor sizes and capacitors required for the DRAM block in one portion of an integrated circuit, while processing a different portion of the integrated circuit to produce the larger transistors, and even analog components such as resistors, required for other applications, in a single piece of silicon. These advances make efficient and compact embedded DRAM arrays even more important.
FIG. 5 depicts a schematic of a typical prior art sense amplifier and a select circuit used with memory cell such as 11 shown in FIG. 1. In FIG. 5, a pre-charge/equalization circuit comprising transistors TN3, TN4 and TN5, and a control line BLEQ, is depicted. This circuit is controlled by the control signal BLEQ and when active, couples a voltage VBL (pre-charge/equalization voltage) to a pair of local bit lines labeled BL and ZBL through MOS transistors TN4 and TN5. In operation, the pre-charge circuit also acts as an equalization circuit, and couples these two nodes together through a pass gate TN3 to ensure the two local bit lines are equal.
The lines BL and ZBL (commonly referred to as “bit line” and “bit line bar”, also commonly called digit lines or DL and DLZ) are coupled to the sense amplifier formed form transistors TB1, TN2, and TP1, TP2, which form a cross coupled latch. In operation the sense amplifier is enabled at a certain time in the memory cycle by applying the correct voltages to lines SP (sense P supply) and SN (sense N supply). These lines are shown extending across the columns formed by the bit lines BL and ZBL to indicate that these lines extend to other sense amplifiers associated with the other bit line pairs in the DRAM array (not visible in this drawing). Typically, the PMOS transistors TP1 and TP2, sometimes referred to as the “pull-up” transistors, are coupled to a positive voltage potential during sensing such as Vdd or Vcc, or sometimes a reduced positive supply such as Vdd/2, while in contrast the NMOS transistors, TN1 and TN2, often referred to as the “pull-down” transistors of the sense amplifier, are coupled to a ground or negative potential voltage during sensing, e.g. Vss level. When the sense amplifier is to sense data from the bit lines, a predetermined voltage is placed on both the P supply line SP and the N supply line SN and the latch formed from the cross coupled inverters (TP1, TN1 and TP2, TN2) within the sense amp senses the small voltage signal present on one of the local bit lines BL, and ZBL. This small voltage results from the discharge of a selected memory cell storage capacitor (selected by the associated word line, not visible in this drawing). The latch formed from the cross coupled inverters then latches the small signal received and amplifies it to a full logic voltage level, which can then be observed by the I/O buffers (not visible in this drawing) that are coupled to the global bit lines and at certain time periods, coupled to the local data lines through the operation of the bit line select circuit described below. The output of the sense amplifier is received on the local bit lines and appears as the bit lines BL and ZBL are spread apart in terms of voltage, one line will go low towards the low logical voltage level, and the other will rise from the initial equalization voltage to the high logical voltage level. It is important to note that only one of the local bit lines receives a voltage from a selected memory cell, the sense amplifier sees the difference between the read data (whether a positive small voltage or a negative small voltage) with respect to the other bit line, which remains at the equalization level, and amplifies that difference to spread the two lines apart.
Transistors TN6 and TN7 are pass gate transistors which couple the local bit lines BL and ZBL to the global bit lines GBL and ZGBL responsive to the bit line select control line SSL. In operation, the control line SSL is activated during a certain portion of the read, or write, cycle. In a read operation, the select control line SSL enables the transistors TN6 and TN7 such that the amplified voltage from the sense amplifier, now present on the local bit lines BL and ZBL, is coupled to the global bit lines GBL and ZGBL. In a write operation, the data from the I/O buffers coupled to the global bit lines GBL and ZGBL is further coupled onto the local bit lines BL and ZBL by the transistors TN6 and TN7, and when the word line for the active memory cell goes inactive, the write data is then stored into the selected memory cell storage capacitor.
In a prior art memory cell read operation, the voltage on the local bit lines must be sufficient to overcome any remaining voltage on the global bit lines when the SSL control couples the pairs of bit lines (local and global bit lines) together. Since the small voltage on the local bit lines from the storage capacitor in a memory cell is insufficient to overcome the external voltage, the timing of the signals operating the select circuit must be such that the select transistors TN6 and TN7 are not enabled by the select control line SSL until the sense amplifier has had sufficient time to sense the small signal voltage from the selected memory cell, and then to amplify the sensed voltage on the local bit lines BL and ZBL.
If a selected memory cell (selected by an active word or row line) is particularly weak, or, the timing of the read cycle is shortened too much, a cell “read disturb” effect error may occur. A memory cell read disturb means that the data stored in the cell may erroneously change value because the voltage appearing on the local bit lines erroneously is changed or “disturbed” by the external voltages being coupled from the global bit lines to the local bit lines. Since DRAM cells have a destructive read out characteristic, each read cycle, which discharges the storage capacitor of a selected cell onto a local bit line, is followed by a “write back” where the capacitor within the selected storage cell is charged again. This charge is provided from the amplified voltage now present on the local bit lines due to the operation of the sense amplifier. However, if during the select part of the read cycle the voltage on the local bit lines is erroneously modified or disturbed, the voltage written back to the storage cell may be incorrect. In that case, for the next read of the particular storage cell, an incorrect data value is retrieved. “Read disturb” or “cell disturb” is a problem well known in the DRAM art.
FIG. 6 is a timing diagram for a prior art DRAM memory cell read operation. In the prior art read operation, a read cycle begins when the word line for a selected memory cell becomes active. In FIG. 6, the word line WL is active when it is low, so the cycle begins when the word line falls below a threshold voltage and ends when it rises back through this voltage. In this example the cycle time is 3.3 nanoseconds, although this is only exemplary for purposes of this description and is not limiting.
In FIG. 6, after the line labeled “word line WL” falls, the local bit lines can be seen to begin to separate from an initial, equalized value. As the cell capacitor is discharged onto the local bit lines, one of the lines will fall below the equalized value and the other will rise above the equalized value. Following this initial time where the cell is accessed onto the local bit lines, the sense amplifier will be enabled. The sense amplifier will then latch this small signal differential voltage and amplify it to cause the local bit line to spread farther apart, which is the differential voltage between the two local bit lines will increase due to the amplification by the sense amplifier. This amplification is seen in FIG. 6, as the time tR begins, the lines labeled “local bit line pair” spread apart over time, to form full logic levels, one line going high, the other going low. After a predetermined time elapses the select control signal, labeled SSL in FIG. 6, becomes active, in this example the line is an active “high” and rises to become active. As the select control line SSL passes through a threshold voltage for the transistors TN6 and TN7, the global bit lines are coupled to the local bit line pair. As can been seen in the timing diagram of FIG. 6, if the global bit lines, or one of them, have a voltage on that line prior to the read cycle, then a read disturb can occur when the local bit line and the global bit line are coupled together. If the sense amplifier has not had sufficient time to develop a strong voltage on the local bit line prior to the SSL active time, this can cause an erroneous operation as discussed above. In this example, it can be seen that a voltage “hump” appears on one of the local bit lines when the value is disturbed by the discharge of the global bit line onto the local bit line. This is shown in FIG. 6.
In prior art approaches to overcome this problem, read disturb errors are typically addressed or prevented by increasing the delay or waiting time before the select control signal is asserted, so that the local bit lines to have time to have a solid voltage developed before the select control line couples the global bit lines to the local bit lines. This approach essentially lengthens the DRAM read cycle, which slows the operation of the DRAM array and so makes higher speed DRAMs impractical to build. This approach recognizes that in the circuit of FIG. 5, the global bit line that is to receive a “low” voltage from one of the local bit lines has to be discharged through the sense amplifier transistor pull down circuit. Even so, some memory cells may have higher charge leakage than others, which results in a “weak” memory cell (the small signal voltage output during a read cycle is smaller) and those cells may still experience a “disturb”. Since these effects may not be completely observable at the time of manufacture, read disturb errors continue to occur in DRAMs even after extensive testing and burn-in cycles are performed to try to eliminate weaker integrated circuits. Read cycle times are therefore extended to try to ensure proper operation of the devices in the field, resulting in slower than desired DRAM operation.
In a write operation, as is known in the prior art, the SSL control line is used to couple the write data present on the global bit lines to the selected local bit line pair, such as BL and ZBL in FIG. 5. During the write cycle, the local bit lines are charged to a full Vcc/Vdd level to make sure a full voltage is stored in the addressed storage cell, and waiting for the full rise time to Vdd of the local bit lines also extends the time of the write cycle in the prior art DRAMs. This write cycle time, which cannot start until the select control lines SSL couple the write data onto the local bit lines through the pass gates TN6 and TN7 in FIG. 5, further slows the operation of the prior art DRAM devices.
The read disturb problem, and the relatively long write and read cycle times of the prior art memory column select circuits, apply to prior art DRAMs, whether implemented as discrete memory integrated circuits, and also to those memory arrays implemented as e-DRAMs embedded in integrated devices. As increasing device integration continues in advanced integrated circuit design, the use of embedded DRAM becomes more prevalent, but stand alone commodity DRAM chips are also still important in the memory chip market. As semiconductor process technologies continue to advance to smaller and smaller minimum feature sizes, the demand for faster DRAM also increases as the switching speed of the logic transistors increases; that is, as processor speeds increase the memory speeds also need to increase to keep up with the processors. In order for the DRAM or e-DRAM to keep up with the processor or circuitry speed in the system, the DRAM cycle times must be shortened.
A need thus exists for improved DRAM circuitry and methods that substantially maintain the layout efficiency and compactness of the prior art approaches while offering an efficient solution to the read disturb problem on the bit lines, while still maintaining proper noise margins and ensuring correct data retention, providing increasingly fast DRAM access times, efficient operation, and efficient use of silicon area for both embedded and discrete DRAM circuits.